Flash memories which are nonvolatile have been used widely as a semiconductor memory device for portable data storage. The price per bit of a flash memory has been coming down year by year and the downward trend is more rapid than the trend expected from the reduction of memory cell size. This is due to ideas for the structure of a memory cell and the introduction of multilevel storage into a memory cell. A prior art of a high density flash memory for use in filing is described in, for instance, F. Arai et al, IEEE International Electron Devices Meeting, 2000, P. 775–778 and T. Kobayashi et al., IEEE International Electron Devices Meeting)”, 2001, pp. 29–32. F. Arai et al, IEEE International Electron Devices Meeting, 2000, pp. 775–778 describes the achievement of a small memory cell area which is being called a NAND type. The latter describes the achievement of multilevel storage operation which performs multi-bit storage by controlling the number of electrons stored into a floating gate, which is being called an AND type. Both have the effect of reducing bit cost.
Moreover, B. Eitan et al., International Conference on Solid State Devices and Materials, 1999, pp. 5822–524 describes an example of another multilevel storage. This is an element in which SiN is used for a memory region and charge injection is performed by hot electrons. What is employed is the phenomena where hot electrons are created in the vicinity of the drain edge and where charges stay around the area where charges are injected because they are trapped at the SiN trap. Both the source edge and the drain edge are used as charge trapping layers by exchanging the voltages applied to the source and drain. Since a large current flows in this programming technique, it is not suitable for use in filing in which multi-bit simultaneous programming is performed because of limitations in the current drivability of the power supply. JP-A No. 156275/2001 discloses program operation by source side injection in which programming is possible by a lower drain current. F. Arai et al, IEEE International Electron Devices Meeting, 2000, pp. 775–778 describes an operation, in which an inversion layer formed underneath the assist electrode is used as a wiring, as a technology which is compatible with the assist electrode for source side injection and a small cell area.
Flash memory has achieved a bit cost reduction greater than the reduction of memory cell size by decreasing the patterning size as a result of ideas for the structure of an element and the introduction of multilevel storage. Additionally, applications which handle big files such as music files and animation, etc. have broadened with the increase in the density of a flash memory. Therefore, it is expected that there will be a rapid increase in demand in the near future for flash memory which has a high density and fast programming speed.
However, a NAND type element structure is coming closer to the area 4F2 per cell which is the logical limitation of a planar structured memory cell, and it is difficult to reduce the cell area by performing some more ideas for the structure. Therefore, it is necessary to promote multilevel storage in the future. At the same time, since it is a means for programming according to the Fowler-Nordheim (hereinafter, it is abbreviated as FN) tunnel, there is a problem that programming is not fast enough and a large voltage has to be used.
On the other hand, an AND type uses a hot electron programming technique, and high-speed programming is possible. It is also suitable for simultaneous programming of many cells because it is hot electron programming according to the method of source side injection. Additionally, since the array structure is connected in parallel and not connected in series such as a NAND type, it is not easily affected by the stored information in another cell and is suitable for multi-bit storage per cell. However, there is a problem. The problem is brought about from the viewpoint of the cell area. That is, since it has an array structure in which the diffusion layers are lying in parallel, the pitch in the direction perpendicular to the word line is not easily decreased caused by the broadening of the diffusion layer and the isolation region.
Y. Sasago et al., IEEE International Electron Devices Meeting, 2003, p. 29–32 discloses, as a means to solve this problem, an operation method in which an inversion layer formed underneath the electrode lying parallel to the data line is used for the wiring.